Extraction of Parasitic Circuit Elements in a Pebb for Application in the Virtual Test Bed
نویسندگان
چکیده
A numerical procedure for extracting parasitic circuit elements using a quasi-static field solver, as part of the Virtual Test Bed (VTB), is discussed. The parasitic inductance and capacitance values obtained from the model are compared to measured values from a low-inductance Power Electronic Building Block (PEBB) module, designed and constructed at Harris Semiconductor.
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تاریخ انتشار 2000